SH7763 Datasheet, PDF (244/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.7.1 Overview of 32-Bit Address Extended Mode
In 32-bit address extended mode, the privileged space mapping buffer (PMB) is introduced. The
PMB maps virtual addresses in the P1 or P2 area which are not translated in 29-bit address mode
to the 32-bit physical address space. In areas which are target for address translation of the TLB
(UTLB/ITLB), upper three bits in the PPN field of the UTLB or ITLB are extended and then
addresses after the TLB translation can handle the 32-bit physical addresses.
As for the cache operation, P1 area is cacheable and P2 area is non-cacheable in the case of 29-bit
address mode, but the cache operation of both P1 and P2 area are determined by the C bit and WT
bit in the PMB in the case of 32-bit address mode.
6.7.2 Transition to 32-Bit Address Extended Mode
This LSI enters 29-bit address mode after a power-on reset. Transition is made to 32-bit address
extended mode by setting the SE bit in PASCR to 1. In 32-bit address extended mode, the MMU
operates as follows.
1. When the AT bit in MMUCR is 0, virtual addresses in the U0, P0, or P3 area become 32-bit
physical addresses. Addresses in the P1 or P2 area are translated according to the PMB
mapping information.
B'10 should be set to the upper 2 bits of virtual page number (VPN[31:30]) in the PMB in
order to indicate P1 or P2 area. The operation is not guaranteed when the value except B'10 is
set to these bits.
2. When the AT bit in MMUCR is 1, virtual addresses in the U0, P0, or P3 area are translated to
32-bit physical addresses according to the TLB conversion information. Addresses in the P1 or
P2 area are translated according to the PMB mapping information.
B'10 should be set to the upper 2 bits of virtual page number (VPN[31:30]) in the PMB in
order to indicate P1 or P2 area. The operation is not guaranteed when the value except B'10 is
set to these bits.
3. Regardless of the setting of the AT bit in MMUCR, bits 31 to 29 in physical addresses become
B'111 in the control register area (addresses H'FC00 0000 to H'FFFF FFFF). When the control
register area is recorded in the UTLB and accessed, B'111 should be set to PPN[31:29].
Rev. 1.00 Oct. 01, 2007 Page 178 of 1956
REJ09B0256-0100