SH7763 Datasheet, PDF (531/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Bit
13
12
11
10, 9
8
Bit Name
RMA
RTA
STA
DEVSEL
MDPE
Initial
Value
0
0
0
01
0
R/W
Description
SH: R/WC Master Abort Receive Status
PCI: R/WC Indicates that the PCIC has terminated a transaction
with a master abort when the PCIC is a master.
0: PCIC has not terminated a transaction with a
master abort
1: PCIC has terminated a transaction with a master
abort
SH: R/WC Target Abort Receive Status
PCI: R/WC Indicates that a transaction is terminated by a target
device with a target abort when the PCIC functions as
a master.
0: Transaction has not been terminated with a target
abort
1: Transaction has been terminated with a target abort
SH: R/WC Target Abort Execution Status
PCI: R/WC Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
0: PCIC has not terminated a transaction with a
target-abort
1: PCIC has terminated a transaction with target-abort
SH: R
PCI: R
DEVSEL Timing Status
Indicate the response timing status of the DEVSEL
signal when the PCIC functions as a target.
00: Fast (not support)
01: Medium
10: Slow (not support)
11: Reserved
SH: R/WC Data parity error
PCI: R/WC Indicates that the PCIC has asserted the PERR signal
or detected the assertion of the PERR signal if the
PCIC functions as a master. Only when the parity
response bit has been set to 1, this bit is set to 1.
0: Data parity error has not been generated
1: Data parity error has been generated
Rev. 1.00 Oct. 01, 2007 Page 465 of 1956
REJ09B0256-0100