SH7763 Datasheet, PDF (628/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
13.5 Usage Notes
13.5.1 Notes on PCIC Target Reading
When the PCIC is used in target mode and all the three conditions below are satisfied, data may be
lost during a PCIC target read.
1. PFCS bit in PCICR = 1 (32-byte pre-fetch enabled)
2. FTO bit in PCICR = 1 (TRDY control enabled)
3. PFE bit in PCICR = 1 (pre-fetch enabled)
For target reading in target mode, at least one of the above three conditions must be cancelled.
13.5.2 Notes on Host Mode
When the PCIC is used while all the five conditions below are satisfied, REQn (n = 3 to 1) with
the lowest priority is masked, thus disabling correct transfers via the PCI bus, which leads to
unstable operation of the PCI bus system.
1. Host mode (MD6 = high)
2. PCI bus master arbitration mode is set to fixed mode (BMAM bit in PCICR = 0)
3. In addition to this LSI (with the PCIC in host mode), two or more external PCI devices that
can be a bus master are connected to the PCI bus.
4. Among the above external devices, there is at least one device (REQm) that does not execute
REQ negation and FRAME assertion simultaneously when a single transaction is requested
(single or burst transfer).
5. There is an external device (REQn; n > m) that can be a bus master with a priority lower than
the priority of the external device (REQm) satisfying condition 4 above.
PCICLK
REQm
GNTm
FRAME
Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and FRAME
Assertion Simultaneously
Rev. 1.00 Oct. 01, 2007 Page 562 of 1956
REJ09B0256-0100