SH7763 Datasheet, PDF (154/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 4 Pipelining
(6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle
I1
I2
ID s1
s2
s3
FS1 FS2 FS3 FS4 FS
(6-13) FLDI0, FLDI1: 1 issue cycle
I1
I2
ID s1
s2
s3
FS1 FS2 FS3 FS4 FS
(6-14) Single-precision floating-point computation: 1 issue cycle
FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG
I1
I2
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
(6-15) Single-precision FDIV/FSQRT: 1 issue cycle
I1
I2
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
FEDS (Divider occupied cycle)
FE3 FE4 FE5 FE6 FS
(6-16) Double-precision floating-point computation: 1 issue cycle
FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS
I1
I2
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
(6-17) Double-precision floating-point computation: 1 issue cycle
FMUL
I1
I2
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
(6-18) Double-precision FDIV/FSQRT: 1 issue cycle
I1
I2
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
FEDS (Divider occupied cycle)
FE3 FE4 FE5 FE6 FS
FE3 FE4 FE5 FE6 FS
Figure 4.2 Instruction Execution Patterns (8)
Rev. 1.00 Oct. 01, 2007 Page 88 of 1956
REJ09B0256-0100