SH7763 Datasheet, PDF (1738/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
38.7.3 Pck0 Clock and Clock Division Ratio Settings
Four types of frequency divided clocks can be used as the clock for A/D conversion.
Since the internal circuit configuration affects the limits of the interface between the analog and
digital sections, be sure to see table 38.6 when setting the Pck0 clock and clock division ratio.
Table 38.6 Relationship between Clock Division Ratio and Usable Pck0 Clock Frequency
Clock Division Ratio
Pck0/4
Pck0/8
Pck0/16
Pck0/32
Pck0 Clock
18 MHz or lower
34 MHz or lower
67 MHz or lower
67 MHz or lower
38.7.4 A/D Conversion Stop
In multi mode or scan mode, A/D conversion does not stop as soon as the setting to halt A/D
conversion has been made. A/D conversion stops as soon as A/D conversion of the data in the
relevant channel has finished.
Rev. 1.00 Oct. 01, 2007 Page 1672 of 1956
REJ09B0256-0100