SH7763 Datasheet, PDF (1092/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.2 Input/Output Pins
Table 26.1 lists the pins used in the I²C bus interface.
Table 26.1 Pin Configuration
Channel Pin Name
I/O
Description
0
IIC0_SCL
I/O
I²C serial clock input/output pin*
IIC0_SDA
I/O
I²C serial data input/output pin*
1
IIC1_SCL
I/O
I²C serial clock input/output pin*
IIC1_SDA
I/O
I²C serial data input/output pin*
Note: * The SCL and SDA pins are open drain pins (3.3 V).
26.3 Register Descriptions
Table 26.2 shows the IIC register configuration. Table 26.3 shows the register state in each
operating mode.
Table 26.2 Register Configuration
Channel Register Name
Abbreviation R/W
Area P4
Area 7
Access
Address*¹ Address*¹ Size
0
Slave control register 0 ICSCR0
R/W H'FFE7 0000 H'1FF7 0000 8
Master control register 0
Slave status register 0
Master status register 0
ICMCR0
ICSSR0
ICMSR0
R/W H'FFE7 0004 H'1FF7 0004 8
R/(W)*² H'FFE7 0008 H'1FF7 0008 8
R/(W)*³ H'FFE7 000C H'1FF7 000C 8
Slave interrupt enable
register 0
ICSIER0
R/W H'FFE7 0010 H'1FF7 0010 8
Master interrupt enable ICMIER0
register 0
R/W H'FFE7 0014 H'1FF7 0014 8
Clock control register 0 ICCCR0 R/W H'FFE7 0018 H'1FF7 0018 8
Slave address register 0 ICSAR0
R/W H'FFE7 001C H'1FF7 001C 8
Master address register 0 ICMAR0 R/W H'FFE7 0020 H'1FF7 0020 8
Receive data register 0 ICRXD0
R/W H'FFE7 0024 H'1FF7 0024 8
Transmit data register 0 ICTXD0
R/W H'FFE7 0024 H'1FF7 0024 8
Rev. 1.00 Oct. 01, 2007 Page 1026 of 1956
REJ09B0256-0100