SH7763 Datasheet, PDF (9/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Contents
Section 1 Overview......................................................................................................................... 1
1.1 Features of the SH7763.......................................................................................................... 1
1.2 Block Diagram ..................................................................................................................... 13
1.3 Pin Arrangement .................................................................................................................. 14
Section 2 Programming Model ............................................................................37
2.1 Data Formats........................................................................................................................ 37
2.2 Register Descriptions ........................................................................................................... 38
2.2.1 Privileged Mode and Banks .................................................................................... 38
2.2.2 General Registers.................................................................................................... 42
2.2.3 Floating-Point Registers.......................................................................................... 43
2.2.4 Control Registers .................................................................................................... 45
2.2.5 System Registers..................................................................................................... 47
2.3 Memory-Mapped Registers.................................................................................................. 51
2.4 Data Formats in Registers .................................................................................................... 52
2.5 Data Formats in Memory ..................................................................................................... 52
2.6 Processing States.................................................................................................................. 53
2.7 Usage Note........................................................................................................................... 55
2.7.1 Notes on Self-Modified Codes................................................................................ 55
Section 3 Instruction Set ......................................................................................57
3.1 Execution Environment ....................................................................................................... 57
3.2 Addressing Modes ............................................................................................................... 59
3.3 Instruction Set ...................................................................................................................... 64
Section 4 Pipelining .............................................................................................79
4.1 Pipelines............................................................................................................................... 79
4.2 Parallel-Executability........................................................................................................... 90
4.3 Issue Rates and Execution Cycles........................................................................................ 94
Section 5 Exception Handling ...........................................................................105
5.1 Summary of Exception Handling....................................................................................... 105
5.2 Register Descriptions ......................................................................................................... 105
5.2.1 TRAPA Exception Register (TRA) ...................................................................... 106
5.2.2 Exception Event Register (EXPEVT)................................................................... 107
5.2.3 Interrupt Event Register (INTEVT)...................................................................... 108
5.3 Exception Handling Functions........................................................................................... 109
Rev. 1.00 Oct. 01, 2007 Page ix of lxvi