SH7763 Datasheet, PDF (1865/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 42 User Debugging Interface (H-UDI)
42.2 Input/Output Pins
Table 42.1 shows the pin configuration for the H-UDI.
Table 42.1 Pin Configuration
Pin Name Function I/O Description
When Not
in Use
TCK
TMS
Clock
Mode
Input
Input
Functions as the serial clock input pin stipulated in
the JTAG standard. Data input to the H-UDI via the
TDI pin or data Output via the TDO pin is performed
in synchronization with this signal.
Mode Select Input
Open*¹
Open*¹
TRST*²
TDI
Reset
Data input
Input
Input
Changing this signal in synchronization with the TCK
signal determines the significance of data input via
the TDI pin. Its protocol conforms to the JTAG
standard (IEEE standard 1149.1).
H-UDI Reset Input
Fixed to
This signal is received asynchronously with a TCK ^{ground or}
signal. Asserting this signal resets the JTAG interface
circuit. When a power is supplied, the TRST pin
should be asserted for a given period regardless of
connected to
the PRESET
pin*³
whether or not the JTAG function is used, which
differs from the JTAG standard.
Data Input
Open*¹
Data is sent to the H-UDI by changing this signal in
synchronization with the TCK signal.
TDO
Data output Output Data Output
Open
ASEBRK/
BRKACK
Emulator I/O
Data is read from the H-UDI in synchronization with
the TCK signal.
Pins for an emulator
Open*¹
AUDSYNC,
AUDCK,
AUDATA3 to
AUDATA0
Emulator
Output Pins for an emulator
Open
MPMD
Chip-mode Input
Selects the operation mode of this LSI, whether
Open
emulation support mode (Low level) or LSI operation
mode (High level).
Notes: 1. This pin is pulled up in this LSI. When using interrupts or resets via the H-UDI or
emulator, the use of external pull-up resistors will not cause any problem.
2. When using interrupts or resets via the H-UDI or emulator, the TRST pin should be
designed so that it can be controlled independently and can be controlled to retain low
level while the PRESET pin is asserted at a power-on reset.
Rev. 1.00 Oct. 01, 2007 Page 1799 of 1956
REJ09B0256-0100