SH7763 Datasheet, PDF (1634/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one
FIFO is empty, IFR0/EP2 EMPTY is set to 1. When ACK is returned from the host after data
transmission is completed, the FIFO used in the data transmission becomes empty. If the other
FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to IER0/EP2 EMPTY and disable
interrupt requests.
Rev. 1.00 Oct. 01, 2007 Page 1568 of 1956
REJ09B0256-0100