SH7763 Datasheet, PDF (1131/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
SCIFn_RXD
Serial receive
data
SPTRR
SPTRR: Read from SCSPTR
Peripheral bus
Figure 27.6 SCIFn_RXD Pin (n = 0, 1)
27.2 Input/Output Pins
Table 27.1 shows the SCIF pin configuration. Since the pin functions are the same in each
channel, the channel number is omitted in the description below.
Table 27.1 Pin Configuration
Pin Name
Function
I/O
Description
SCIFn_SCK (n = 0, 1) Serial clock pin
I/O
Clock input/output
SCIFn_RXD (n = 0, 1) Receive data pin
Input
Receive data input
SCIFn_TXD (n = 0, 1)
SCIFn_CTS (n = 0, 1)
SCIFn_RTS (n = 0, 1)
Transmit data pin
Modem control pin
Modem control pin
Output
I/O
I/O
Transmit data output
Transmission enabled
Transmission request
Note: These pins are made to function as serial pins by performing SCIF operation settings with
the C/A bit in SCSMR, the TE, RE, CKE1, and CKE0 bits in SCSCR, and the MCE bit in
SCFCR. Break state transmission and detection can be set in SCSPTR of the SCIF.
Rev. 1.00 Oct. 01, 2007 Page 1065 of 1956
REJ09B0256-0100