SH7763 Datasheet, PDF (1621/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.39 Timer Register (TMRH/TMRL)
TMRH/TMRL is a 16-bit timer which is operated with a peripheral clock φ. Measuring the SOF
packet reception interval enables the SOF packet break to be detected.
The timer is operated, stopped, and cleared according to the settings of the control register 1
(CTLR 1)
TMRH/TMRL is handled as a 16-bit (TMR[15:0]) register in the USBF which consists of
TMR[15:8] bits in TMRH and TMR[7:0] bits in TMRL. Although TMRH can be read directly,
TMRL is read via an 8-bit temporary register. Therefore, the registers should be read in the order
of TMRH and TMRL in byte units. TMRL cannot be read singly.
• TMRH
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TMR[15:8]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
7 to 0 TMR[15:8]
Initial value R/W Description
Undefined R Reserved
These bits are always read as undefined value. The
write value should always be 0.
0
R/W Upper Eight Bits of Count Value
Rev. 1.00 Oct. 01, 2007 Page 1555 of 1956
REJ09B0256-0100