SH7763 Datasheet, PDF (1460/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
33.3.1 Control and Status Register (HACCR)
HACCR is a 32-bit read/write register for controlling input/output and monitoring the interface
status.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−−− − −−−− −−−−− − −
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CR _{− − − −} CDRT WMRT _{− − −} ST _{− − − − −}
Initial value:
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W: R R R R W W R R R R W R R R R R
Initial
Bit
Bit Name Value R/W
31 to 16 
All 0 R
15
CR
0
R
14 to 12 
11
CDRT
All 0 R
0
W
Description
Reserved
Always 0 for read and write.
Codec Ready
0: The HAC-connected codec is not ready.
1: The HAC-connected codec is ready.
Reserved
Always read as 0. Write prohibited.
HAC Cold Reset
Use a cold reset only after power-on, or only to exit
from the power-down mode by the power-down
command.
[Write]
0: Always write 0 to this bit before writing 1 again.
1: Performs a cold reset on the HAC.
[Read]
Always read as 0.
Rev. 1.00 Oct. 01, 2007 Page 1394 of 1956
REJ09B0256-0100