SH7763 Datasheet, PDF (1195/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Initial
Bit
Bit Name Value R/W Description
5
PE
0
R/W Parity Enable
In asynchronous mode, selects whether or not parity bit
addition is performed in transmission, and parity bit
checking is performed in reception. In clocked
synchronous mode, parity bit addition and checking is
disabled regardless of the PE bit setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled*
Note: *
When the PE bit is set to 1, the parity (even or
odd) specified by the O/E bit is added to
transmit data before transmission. In
reception, the parity bit is checked for the
parity (even or odd) specified by the O/E bit.
4
O/E
0
R/W Parity Mode
Selects either even or odd parity for use in parity
addition and checking. In asynchronous mode, the O/E
bit setting is only valid when the PE bit is set to 1,
enabling parity bit addition and checking. In clocked
synchronous mode or when parity addition and
checking is disabled in asynchronous mode, the O/E bit
setting is invalid.
0: Even parity
1: Odd parity
When even parity is set, parity bit addition is performed
in transmission so that the total number of 1-bits in the
transmit character plus the parity bit is even. In
reception, a check is performed to see if the total
number of 1-bits in the receive character plus the parity
bit is even.
When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1-bits in the
transmit character plus the parity bit is odd. In
reception, a check is performed to see if the total
number of 1-bits in the receive character plus the parity
bit is odd.
Rev. 1.00 Oct. 01, 2007 Page 1129 of 1956
REJ09B0256-0100