SH7763 Datasheet, PDF (318/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − − − − − − − ^{IM00 IM01 IM02 IM03 IM04 IM05 IM06 IM07}
Initial value:
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−− −− −− −−−− −−−− −−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Bit
Bit Name
31
IM00
30
IM01
29
IM02
28
IM03
27
IM04
26
IM05
25
IM06
24
IM07
23 to 0 
Initial
Value
1
1
1
1
1
1
1
1
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Sets masking of an
independent interrupt
request of IRQ0.
Sets masking of an
independent interrupt
request of IRQ1.
[When reading]
0: Interrupts are accepted
1: Interrupts are masked
[When writing]
0: Invalid
Sets masking of an
independent interrupt
request of IRQ2.
1: Interrupts are masked
Sets masking of an
independent interrupt
request of IRQ3.
Sets masking of an
independent interrupt
request of IRQ4.
Sets masking of an
independent interrupt
request of IRQ5.
Sets masking of an
independent interrupt
request of IRQ6.
Sets masking of an
independent interrupt
request of IRQ7.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 252 of 1956
REJ09B0256-0100