SH7763 Datasheet, PDF (1024/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.8 shows an example of transmission flow.
Transmission flowchart
This LSI + memory E-DMAC
Transmit FIFO
GETHER
initalization
Transmit
descriptor and
transmit buffer
setting
Start of transmission
Transmit descriptor read
Transmit data transfer
Transmit descriptor
write-back
Transmit descriptor
read
Transmit data transfer
Transmit descriptor
write-back
Transmission
completed
E-MAC
Ethernet
GMII/MII/RMIi
Frame transmission
[Legend]
GETHER initialization: Executes a software reset with the SWR bit in EDMR set to 1.
Transmit descriptor and transmit setting: Setes transmit descriptors and transmit buffer, and sets E-MAC
and E-DMAC registeers, then writes 11 to the TE bit in ECMR
and the TR bit in EDTRR.
Start of transmission: Occurs when 1 is written to the TE bit in ECMR and 11 is written to the TR bit in EDTRR.
Transmit descriptor read: The E-DMAC reads a transmit descriptor.
Transmit data transfer : Writes transmit dara to the transmit FIFO by using DMA transfer by the E-DMAC
Transmit descriptor write-back: The E-DMAC writes 0 to the TACT bit and writes the transmit status to the transmit descriptor.
Figure 23.8 Sample Transmission Flowchart (Single-Frame/Two-Description)
Rev. 1.00 Oct. 01, 2007 Page 958 of 1956
REJ09B0256-0100