SH7763 Datasheet, PDF (975/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.73 Receive Descriptor List Start Address Register (RDLAR)
RDLAR is a 32-bit readable/writable register that specifies the start address of the receive
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bits in EDMR. This register must not be modified during reception.
Modifications to this register should only be made while reception is disabled by the RR bit (= 0)
in the E-DMAC receive request register (EDRRR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDLA[31:15]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RDLA[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
RDLA[31:0]
Initial
Value
All 0
R/W Description
R/W Receive Descriptor Start Address
The lower bits are set according to the specified
descriptor length.
16-byte boundary: RDLA[3:0] = 0000
32-byte boundary: RDLA[4:0] = 00000
64-byte boundary: RDLA[5:0] = 000000
Rev. 1.00 Oct. 01, 2007 Page 909 of 1956
REJ09B0256-0100