SH7763 Datasheet, PDF (306/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Source
Number of
Sources
(Max.) Priority
INTEVT
Remarks
On-chip GPIO 4
module
interrupts*²
Setting value of INT2PRI0 H'F80
to INT2PRI13
H'FA0
H'FC0
CH0
CH1
CH2
H'FE0 CH3
Notes: 1. Since the IRL interrupt request by IRL[3:0] (IRQ3/IRL3 to IRQ0/IRL0 pins) and IRL
interrupt request by IRL[7:4] (IRQ7/IRL7 to IRQ4/IRL4 pins) have the same INTEVT
codes, it is impossible to distinguish the former from the latter. Note that there is no
flags in this LSI for distinguishing between them.
2. ITI:
Interval timer interrupt
TUNI0 to TUNI5:
TMU channel 0 to 5 under flow interrupt
TICPI2:
TMU channel 2 input capture interrupt
DMINT0 to DMINT11: DMAC channel 0 to 5 transfer end interrupt
DMAE:
DMAC address error interrupt (channel 0 to 5)
ERI0, ERI1:
SCIF channel 0, 1 receive error interrupt
RXI0, RXI1:
SCIF channel 0, 1 receive data full interrupt
BRI0, BRI1:
SCIF channel 0, 1 break interrupt
TXI0, TXI1:
SCIF channel 0, 1 transmission data empty interrupt
3. The SECURITY is not incorporated in the R5S77631. Therefore, the INTEVT code is
reserved in the R5S77631.
9.2 Input/Output Pins
Table 9.2 shows the pin configuration.
Table 9.2 INTC Pin Configuration
Pin Name
NMI
IRQ3/IRL3 to
IRQ0/IRL0
Function
I/O
Nonmaskable interrupt
input pin
Input
External interrupt input pin Input
Description
Nonmaskable interrupt request
signal input
Interrupt request signal input
IRL [3:0] 4-bit level-encoded
interrupt input when ICR0.IRLM0 = 0
IRQ3 to IRQ0 individual interrupt
input when ICR0.IRLM0 = 1
Rev. 1.00 Oct. 01, 2007 Page 240 of 1956
REJ09B0256-0100