SH7763 Datasheet, PDF (1096/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
Bit
Bit Name Initial Value R/W Description
0
FNA
0
R/W Forced Non Acknowledgement
In the slave receive mode, the level of this bit is
sent to the transmitting device as the
acknowledge signal. This bit is set to 0 during the
period that the data packet is being received, and
set to 1 on completion of data reception.
Forced non acknowledgement is returned to the
master during slave reception.
When the slave has received the last byte of data
in a data packet, the slave communicates with
the master by sending a nack, meaning that the
acknowledgement is not driven. The master
issues a stop on the bus after receiving a nack.
The setting of this bit does not affect the
acknowledgement of the slave address.
Rev. 1.00 Oct. 01, 2007 Page 1030 of 1956
REJ09B0256-0100