SH7763 Datasheet, PDF (1180/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Table 27.8 SCIF Interrupt Sources
Interrupt
Source
Description
DMAC
Activation
Priority on
Reset Release
ERI
Interrupt initiated by receive error flag (ER)
Not possible
High
RXI
Interrupt initiated by receive FIFO data full flag Possible
(RDF) or receive data ready flag (DR)*
BRI
Interrupt initiated by break flag (BRK) or overrun Not possible
error flag (ORER)
TXI
Interrupt initiated by transmit FIFO data empty Possible
flag (TDFE)
Low
Note: * An RXI interrupt by setting of the DR flag is available only in asynchronous mode.
Rev. 1.00 Oct. 01, 2007 Page 1114 of 1956
REJ09B0256-0100