SH7763 Datasheet, PDF (1592/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.17 EP0o Data Register (EPDR0o)
EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data
other than setup commands. When data is received normally, EP0oTS in interrupt flag register 0 is
set, and the number of receive bytes is indicated in the EP0o receive data size register. After the
data has been read, setting EP0oRDFN in the trigger register enables the next packet to be
received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
D[7:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 8 
7 to 0 D[7:0]
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Undefined R Data register for control-out transfer
Rev. 1.00 Oct. 01, 2007 Page 1526 of 1956
REJ09B0256-0100