SH7763 Datasheet, PDF (214/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.2.2 Page Table Entry Low Register (PTEL)
PTEL is used to hold the physical page number and page management information to be recorded
in the UTLB by means of the LDTLB instruction. The contents of this register are not changed
unless a software directive is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPN
Initial value: 0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PPN
V SZ1 PR1 PR0 SZ0 C
D SH WT
Initial value:
0
R/W: R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 29 
All 0 R
28 to 10 PPN
9


R/W
0
R
8
V

R/W
7
SZ1

R/W
6
PR1

R/W
5
PR0

R/W
4
SZ0

R/W
3
C

R/W
2
D

R/W
1
SH

R/W
0
WT

R/W
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Physical Page Number
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
Page Management Information
The meaning of each bit is same as that of
corresponding bit in Common TLB (UTLB).
For details, see section 6.3, TLB Functions.
Rev. 1.00 Oct. 01, 2007 Page 148 of 1956
REJ09B0256-0100