SH7763 Datasheet, PDF (336/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Bit
Bit Name
31 to 26 —
Initial
Value
All 0
25
SCIF2
0
24
USBF
0
23, 22 —
All 0
21
STIF1
0
20
STIF0
0
19, 18 —
All 0
17
USBH
0
16
GETHER 0
15
PCC
0
14
—
0
13
—
0
12
ADC
0
11
TPU
0
10
SIM
0
R/W Function
Description
R This bit is always read as 0. Indicates interrupt
The write value should
sources for each
always be 0.
peripheral module
R
Indicates SCIF2 interrupt
source
(INT2A01 is not affected
by the state of the
interrupt mask register).
R
Indicates USBF interrupt
source
0: No interrupts
1: Interrupts are
R
These bits are always read _generated
as 0. The write value should
always be 0.
Note: Reading the
INTEVT code
R Indicates STIF1 interrupt
notified to the CPU
source
directly can identify
R Indicates STIF0 interrupt
source
R Undefined values are read
from these bits. The write
interrupt sources.
In this case,
reading INT2A01 is
not necessary.
value should always be 0
R Indicates USBH interrupt
source
R Indicates GETHER interrupt
source
R Indicates PCC interrupt
source
R This bit is always read as 0.
The write value should
always be 0.
R Undefined value is read
from this bit.
The write value should
always be 0.
R Indicates ADC interrupt
source
R Indicates TPU interrupt
source
R Indicates SIM interrupt
source
Rev. 1.00 Oct. 01, 2007 Page 270 of 1956
REJ09B0256-0100