SH7763 Datasheet, PDF (718/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
17.3.3 Watchdog timer Base Stop Time Register (WDTBST)
WDTBST is a readable/writable 32-bit register that clears WDTBCNT. Use a longword access to
clear the WDTBCNT, with H'A5 in the bits 31 to 24. The reading value of bits WDTBST is
always H'0000 0000.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
(Given code)
−− −−− −− −
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− −−− − −− −−− −− −− −−
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI R/W: R R R R R R R R R R R R R R R R
Bit
31 to 24
Bit Name
(Given
code)
Initial
Value
R/W
R/W
H'00
23 to 0 
R
All 0
Description
Reserved (Given code for writing)
These bits are always read as H'00. To write to this
register, the write value must be H'55.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 652 of 1956
REJ09B0256-0100