SH7763 Datasheet, PDF (1959/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.19 SSI Interface Module Signal Timing
Table 43.32 SSI Interface Module Signal Timing
Conditions:
V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
Symbol Min.
Output cycle time
Input cycle time
Input high level width/Output high
level width
t
60
OSCK
t_ISCK
60
t_IHC/t_OHC
15
Input low level width/Output low level t /t
15
ILC OLC
width
SSI_SCK output rise time
t
—
RC
SSI_SDATA/WS output delay time t_DTR
—
SSI_SDATA/WS input setup time t
10
SR
SSI_SDATA/WS input hold time
t_HTR
10
Max.
960
3300
—
Unit Remarks Figure
ns output
43.73
ns input
43.73
ns input, output 43.73
— ns input, output 43.73
10 ns output
43.73
25
ns transmit
43.74, 43.75
— ns receive
43.76, 43.77
— ns receive
43.76, 43.77
V_IH,
SSI_SCK
V_OH
V_IL, V_OL
t_OHC
t_IHC
V_IH,
V_OH
V_IL,
V_OL
t_OLC
t_ILC
t_ISCK, t_OSCK
t_RC
V_IH, V_OH
V_IL, V_OL
Figure 43.73 SSI Clock Input/Output Timing
SSI_SCK
t_DTR
SSI_WS,
SSI_SDATA
Figure 43.74 SSI Transmit Timing (1)
Rev. 1.00 Oct. 01, 2007 Page 1893 of 1956
REJ09B0256-0100