SH7763 Datasheet, PDF (1854/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
• When the match condition is satisfied at the operand access cycle for the first channel in the
sequence whereas the match condition is satisfied at the instruction fetch cycle for the second
channel in the sequence:
Instruction B is 0 to five instructions after
instruction A
Instruction B is six or more instructions after
instruction A
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
• When the match condition is satisfied at the operand access cycle for both the first and second
channels in the sequence:
Instruction B is 0 to five instructions after
instruction A
Instruction B is six or more instructions after
instruction A
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
41.3.6 Program Counter Value to be Saved
When a break has occurred, the address of the instruction to be executed when the program
restarts is saved in the SPC then the exception handling state is initiated. A unique instruction
causing a break can be identified unless the data value is included in the match conditions.
1. When the instruction fetch cycle (before instruction execution) is specified as the match
condition:
The address of the instruction which has satisfied the match conditions is saved in the SPC.
The instruction which has satisfied the match conditions is not executed, but a break occurs
instead. However, if the match conditions are satisfied for the delayed slot instruction, the
address of the delayed branch instruction is saved in the SPC.
2. When the instruction fetch cycle (after instruction execution) is specified as the match
condition:
The address of the instruction immediately after the instruction which has satisfied the match
conditions is saved in the SPC. The instruction which has satisfied the match conditions is
executed, then a break occurs before the next instruction. If the match conditions are satisfied
for the delayed branch instruction or its delayed slot, these instructions are executed and the
address of the branch destination is saved in the SPC.
Rev. 1.00 Oct. 01, 2007 Page 1788 of 1956
REJ09B0256-0100