SH7763 Datasheet, PDF (1679/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
Bit
9
8
7 to 0
Bit Name
VSINTS
VEINTS

Initial Value R/W
0
R/W
0
R/W
All 0
R
Description
Vsync Start Interrupt State
Indicates the LCDC's Vsync start interrupt handling
state. This bit is set to 1 at the time a Vsync start
interrupt is generated. During the Vsync start
interrupt handling routine, this bit should be cleared
by writing 0 to it.
0: LCDC did not generate a Vsync start interrupt or
has been informed that the generated Vsync start
interrupt has completed
1: LCDC has generated a Vsync start interrupt and
has not yet been informed that the generated
Vsync start interrupt has completed
Vsync End Interrupt State
Indicates the LCDC's Vsync end interrupt handling
state. This bit is set to 1 at the time a Vsync end
interrupt is generated. During the Vsync end
interrupt handling routine, this bit should be cleared
by writing 0.
0: LCDC did not generate a Vsync end interrupt or
has been informed that the generated Vsync end
interrupt has completed
1: LCDC has generated a Vsync end interrupt and
has not yet been informed that the generated
Vsync interrupt has completed
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1613 of 1956
REJ09B0256-0100