SH7763 Datasheet, PDF (1287/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Table 29.6 Serial Transfer Modes
TRMD[1:0]
Transfer Mode SIOF_SYNC
Bit Delay
Control Data*
00
Slave mode 1 Synchronous pulse SYNCDL bit
Slot position
01
Slave mode 2 Synchronous pulse
Secondary FS
10
Master mode 1 Synchronous pulse
Slot position
11
Master mode 2 L/R
No
Not supported
Note: * The control data method is valid only when the FL bit is specified as B'1xxx (x: don't
care).
(2) Frame Length
The length of the frame to be transferred by the SIOF is specified by the bits FL[3:0] in SIMDR.
Table 29.7 shows the relationship between the bits FL[3:0] settings and frame length.
Table 29.7 Frame Length
FL[3:0]
Slot Length
00XX
8
0100
8
0101
8
0110
8
0111
8
10XX
16
1100
16
1101
16
1110
16
1111
16
Note: X: Don't care.
Number of Bits
in a Frame
8
16
32
64
128
16
32
64
128
256
Transfer Data
8-bit monaural data
8-bit monaural data
8-bit monaural data
8-bit monaural data
8-bit monaural data
16-bit monaural data
16-bit monaural stereo data
16-bit monaural stereo data
16-bit monaural stereo data
16-bit monaural stereo data
Rev. 1.00 Oct. 01, 2007 Page 1221 of 1956
REJ09B0256-0100