SH7763 Datasheet, PDF(659/2026 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7763 Datasheet, PDF (659/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

◁

Section 14 Direct Memory Access Controller (DMAC)

When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer

destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer

request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive

data register. These conditions also apply to the SCIF1, SCIF2, HAC USBF, SSI0 to SSI3,

MMCIF, SIM, SIOF0 to SIOF2, STIF0, and STIF1.

Table 14.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0]

CHCR

RS[3:0]

1000

DMARS

MID

RID

000000 11

000001 11

000010 11

000011 11

000100 11

001000 01

10

001010 01

10

010000 01

10

010001 01

10

010100 01

10

011100 11

11

DMA Transfer

Request

DMA Transfer

Source

Request Signal

Source

CMT

Compare-match transfer

Any

channel 0

request

CMT channel Compare-match transfer

Any

1

request

CMT channel Compare-match transfer

Any

2

request

CMT channel Compare-match transfer

Any

3

request

CMT channel Compare-match transfer

Any

4

request

SCI F0

TXI (transmit FIFO data

Any

transmitter empty interrupt)

SCIF0

receiver

RXI (receive FIFO data

full interrupt)

SCFRDR0

SCI F1

TXI (transmit FIFO data

Any

transmitter empty interrupt)

SCIF1

receiver

RXI (receive FIFO data

full interrupt)

SCFRDR1

SCIF2

TXI (transmit FIFO data

Any

transmitter empty interrupt)

SCIF2

receiver

RXI (receive FIFO data full SCFRDR2

interrupt)

HAC

transmitter

Transmit data empty request Any

HAC

receiver

Receive data is not read

HACPCML,

HACPCMR

USB

transmitter

Transmit data empty request Any

USB

receiver

Receive data full request EPDR

SSI0

transmitter

Transmit mode : DMRQ = 1 Any

(Transmit data empty

request)

SSI0

receiver

Receive mode : DMRQ = 1 SSIRDR

(Receive data is not read)

Destination

Any

Bus

Mode

Cycle

steal

Any

Any

Any

Any

SCFTDR0

Any

SCFTDR1

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Any

SCFTDR2

Any

HACPCML,

HACPCMR

Any

EPDR

Any

SSIRDR

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Cycle

steal

Any

Cycle

steal

Rev. 1.00 Oct. 01, 2007 Page 593 of 1956

REJ09B0256-0100

▷