SH7763 Datasheet, PDF (1275/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.3.9 Interrupt Enable Register (SIIER)
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each
bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an
interrupt.
BIt:
Initial value:
R/W:
15
TD
MAE
0
R/W
14
TCR
DYE
0
R/W
13
TFE
MPE
0
R/W
12
TDR
EQE
0
R/W
11
RD
MAE
0
R/W
10
RC
RDYE
0
R/W
9
RF
FULE
0
R/W
8
RD
REQE
0
R/W
7
—
0
R/W
6
—
0
R/W
54
SA FS
ERRE ERRE
00
R/W R/W
3
TF
OVFE
0
R/W
2
TF
UDFE
0
R/W
1
RF
UDFE
0
R/W
0
RF
OVFE
0
R/W
Initial
Bit
Bit Name Value R/W Description
15
TDMAE
0
R/W Transmit Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The TDREQE bit can be set as
transmit interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
14
TCRDYE 0
R/W Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
13
TFEMPE 0
R/W Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
12
TDREQE 0
R/W Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer
requests
1: Enables interrupts due to transmit data transfer
requests
11
RDMAE 0
R/W Receive Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The RDREQE bit can be set as
receive interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
Rev. 1.00 Oct. 01, 2007 Page 1209 of 1956
REJ09B0256-0100