SH7763 Datasheet, PDF (381/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 10 SuperHyway Bus Bridge (SBR)
10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV)
SBRIVCLV sets the priority levels used when SuperHyway bus access requests from the
SECURITY, GETHER, and USBH coincide.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
SEC GEC0 GEC1
LV LV LV
—
—
—
USBH
LV
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R/W R/W R/W R R R R/W
Bit
Bit Name
31 to 7 
Initial
Value
All 0
6
SECLV 0
5
GEC0LV 0
4
GEC1LV 0
3 to 1 
All 0
0
USBHLV 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W SECURITY Access Priority Level
0: Level 3
1: Level 2
R/W GETHER0 Access Priority Level
0: Level 3
1: Level 2
R/W GETHER1 Access Priority Level
0: Level 3
1: Level 2
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W USBH Access Priority Level
0: Level 3
1: Level 2
Rev. 1.00 Oct. 01, 2007 Page 315 of 1956
REJ09B0256-0100