SH7763 Datasheet, PDF (813/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 Compare Match Timer (CMT)
Section 21 Compare Match Timer (CMT)
This LSI includes a 32-bit compare match timer (CMT) of five channels (channel 0 to channel 4).
21.1 Features
• 16 bits/32 bits can be selected.
• Each channel is provided with an auto-reload up counter.
• All channels are provided with 32-bit constant registers and 32-bit up counters that can be
written or read at any time.
• Allows selection among three counter input clocks for channel 0 to channel 4:
 Peripheral clock (Pck0): 1/8, 1/32, and 1/128
• One-shot operation and free-running operation are selectable.
• Allows selection of compare match or overflow for the interrupt source.
• Generate a DMA transfer request when compare match or overflow occurs in channels 0 to 4.
• Module standby mode can be set.
Rev. 1.00 Oct. 01, 2007 Page 747 of 1956
REJ09B0256-0100