SH7763 Datasheet, PDF (561/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
7
APEDI
0
SH: R/WC Address Parity Error Detection Interrupt
PCI: R
Indicates an address parity error has been detected.
When both the PER and SERRE bits in the PCI
command register are set to 1, an address parity
error is detected.
0: Address parity error detection interrupt does not
occur
[Clear condition]
Write 1 to this bit (write clear).
1: Address parity error detection interrupt occurs
[Set condition]
When an address parity error detection interrupt
occurs.
6
SEDI
0
SH: R/WC SERR Detection Interrupt
PCI: R
Indicates that the assertion of the SERR signal has
been detected when the PCIC operates in host bus
bridge mode.
0: SERR detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: SERR detection interrupt occurs
[Set condition]
When a SERR detection interrupt occurs.
5
DPEITW 0
SH: R/WC Data Parity Error Interrupt for Target Write
PCI: R
Indicates that a data parity error has been detected
during a target write access (only detected when
PCICMD.PER is set to 1) when the PCIC functions
as a target.
0: Data parity error detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Data parity error detection interrupt occurs
[Set condition]
When a data parity error detection interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 495 of 1956
REJ09B0256-0100