SH7763 Datasheet, PDF (43/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation
(Local Address Space 0/1) .................................................................................... 539
Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ........ 540
Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus
(Non-Byte Swapping: TBS = 0)............................................................................ 542
Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus
(Non-Byte Swapping: TBS = 1)............................................................................ 543
Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus......... 545
Figure 13.15 Address Generation for Type 0 Configuration Access.......................................... 547
Figure 13.16 PCI Local Bus Power Down State Transition ....................................................... 550
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)........................................ 551
Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single)......................................... 552
Figure 13.19 Master Write Cycle in Normal Mode (Burst)........................................................ 553
Figure 13.20 Master Read Cycle in Normal Mode (Burst)......................................................... 554
Figure 13.21 Target Read Cycle in Normal Mode (Single)........................................................ 556
Figure 13.22 Target Write Cycle in Normal Mode (Single)....................................................... 557
Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) ............................ 558
Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) ........................... 559
Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping) .................. 560
Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping)..... 561
Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and
FRAME Assertion Simultaneously....................................................................... 562
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.1 Block Diagram of DMAC ....................................................................................... 566
Figure 14.2 Round-Robin Mode................................................................................................. 596
Figure 14.3 Changes in Channel Priority in Round-Robin Mode............................................... 597
Figure 14.4 Data Flow of Dual Address Mode........................................................................... 598
Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)................................. 599
Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1
(DREQ Low Level Detection) ................................................................................ 600
Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2
(DREQ Low Level Detection) ................................................................................ 601
Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode
(DREQ Low Level Detection) ................................................................................ 601
Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .... 602
Figure 14.10 Bus State when Multiple Channels are Operating ................................................. 606
Figure 14.11 DMA Transfer Flowchart ...................................................................................... 607
Figure 14.12 Reload Mode Transfer........................................................................................... 609
Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 610
Rev. 1.00 Oct. 01, 2007 Page xliii of lxvi