SH7763 Datasheet, PDF (819/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 Compare Match Timer (CMT)
Initial
Bit
Bit Name Value R/W Description
13 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
CMS
0
R/W Compare Match Timer Counter Size
Selects whether the compare match timer counter
(CMCNT) is used as a 16-bit counter or a 32-bit counter.
This setting becomes the valid size for the compare
match timer constant register (CMCOR).
0: Operates as a 32-bit counter
1: Operates as a 16-bit counter
8
CMM
0
R/W Compare Match Mode
Selects one-shot operation or free-running operation of
the counter.
0: One-shot operation
1: Free-running operation
7, 6
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5, 4
CMR[1:0] 00
R/W Compare Match Request
Selects enable or disable for a DMA transfer request or
internal interrupt request in a compare match.
00: Disables a DMA transfer request and internal
interrupt request
01: Enables DMA transfer request
10: Enables an internal interrupt request
11: Setting prohibited
3
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 753 of 1956
REJ09B0256-0100