SH7763 Datasheet, PDF (340/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.17 Interrupt Source Register 11 (Mask State is affected) (INT2A11)
INT2A11 (mask state is affected) is a 32-bit read-only register that indicates interrupt source
modules. Note that if interrupt masking is set in the interrupt mask register, INT2A11 does not
indicate a source module in a corresponding bit. To check whether interrupts are generated,
regardless of the state of the interrupt mask register, use INT2A01.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−
−
−
−
− − ^{SCIF2 USBF}
− − ^{STIF1 STIF0}
− ^USBH
GETH
ER
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
15 14
PCC _−
0
0
RR
13 12 11 10 9
8
7
6
− − ^{ADC TPU SIM SIOF2 SIOF1 LCDC}
0
0
0
0
0
0
0
0
RRRRRRRR
Note: * This bit is reserved in the R5S77631.
5
4
3
2
1
0
IIC1
IIC0
SSI3
SSI2
SSI1
SECU
RITY*
0
0
0
0
0
0
RRRRRR
Initial
Bit
Bit Name Value
31 to 26 —
All 0
25
SCIF2 0
24
USBF
0
23, 22 —
All 0
21
STIF1
0
20
STIF0
0
19, 18 —
All 0
R/W
R
R
R
R
R
R
R
Function
Description
These bits are always read as
0. The write value should
always be 0.
Indicates SCIF2 interrupt
source
Indicates USBF interrupt
source
These bits are always read as
0. The write value should
always be 0.
Indicates STIF1 interrupt
source
Indicates STIF0 interrupt
source
These bits are always read as
0. The write value should
always be 0.
Indicates interrupt
sources for each
peripheral module
(INT2A11 is affected
by the state of the
interrupt mask
register).
0: No interrupts
1: Interrupts are
generated
Note: Reading the
INTEVT code
notified to the
CPU directly can
identify interrupt
sources. In this
case, reading
INT2A11 is not
necessary.
Rev. 1.00 Oct. 01, 2007 Page 274 of 1956
REJ09B0256-0100