SH7763 Datasheet, PDF (539/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(14) PCI Memory Base Address Register 0 (PCIMBAR0)
This register packages the memory space base address register of the PCI configuration register
that is prescribed with PCI local bus specification.
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBA (upper)
MBA (lower)
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
PCI R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MBA (lower)
LAP
LAT
ASI
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 20 MBA
(upper)
Initial
Value
H'000
R/W
SH: R/W
PCI: R/W
19 to 4 MBA
(lower)
3
LAP
H'0000 SH: R
PCI: R
0
SH: R
PCI: R
Description
Memory Space 0 Base Address (upper 12 bits)
Specifies the upper 12 bits of memory base address
that corresponds the local address space 0
(SuperHyway bus address space of this LSI).
Update value
PCILSR [28:20]
0 0000 0000
0 0000 0001
0 0000 0011
|
0 1111 1111
1 1111 1111
Address space Effective bit of
MBA (upper)
1 Mbyte
[31:20]
2 Mbytes
[31:21]
4 Mbytes
[31:22]
|
|
256 Mbytes [31:28]
512 Mbytes [31:29]
Memory Space 0 Base Address (lower 16 bits)
These bits are fixed H'0000 by hardware.
Prefetch Control
Indicates whether or not local address space 0 is
prefetchable.
0: Not prefetchable
1: Prefetchable (not supported)
Rev. 1.00 Oct. 01, 2007 Page 473 of 1956
REJ09B0256-0100