SH7763 Datasheet, PDF (682/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
The transfer destination is the LBSC space and the DACK and TEND are output during the write
cycle:
(1) Set B'001 to B'111 (i.e., other than 000) to the IWW bits in CSnBCR
Note: * The transfer source is the LBSC space and the DACK is output during the read cycle or
the transfer destination is the LBSC space and the DACK is output during the write
cycle. And then specifies no idle cycle (CSnBCR.IWRRD, IWRRS, IWW are cleared
to B'000). Note that the case that both the transfer source and the transfer destination
are the LBSC spaces, does not apply this.
Tables 14.12 to 14.15 show the number of the bus cycles generated in each DMA transfer and the
register settings for the LBSC space. With these settings, CSn is not negated even if multiple bus
cycles are generated.
Note that, in the following settings, when either the transfer source or the transfer destination is
the LBSC space, to avoid the DACK is asserted ceaselessly during between the two or more times
DMA transfer, set B'001 to B'111 to the IWRRD, IWRRS or IWW bits in CSnBCR. In this
setting, if the 16-byte DMA transfer is performed, multiple bus cycles are generated and the CSn
is negated between bus cycles, the DREQ signal is not sampled correctly and malfunction may
occur.
Rev. 1.00 Oct. 01, 2007 Page 616 of 1956
REJ09B0256-0100