SH7763 Datasheet, PDF (483/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.4.1 Memory Interface Mode Register (MIM)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
BOMODE
PC
KE
SEL R
FS MODE
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R/W R R R R R R R R R R R/W R
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRI[12:0]
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LOCK
DRE
END
IAN
DLLEN
DCE
Initial value:
0
0
0
0
0
0
0
0
0
0
0
R/W:
R R R R R R R/W R R R R R R/W R R R/W
Note: * Depends on the setting of external pins (MD5).
Initial
Bit
Bit Name Value R/W Description
63 to 49 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
48

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
47, 46 BOMODE1, All 0
BOMODE0
R/W Access Mode Switch
Switch access modes for the DDR-SDRAM.
The DDRIF supports two DDR-SDRAM access modes.
For details on the operation in each mode, see section
12.5.4, DDR-SDRAM Access Mode.
00: Bank open mode
01: Bank close mode
Other than above: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 417 of 1956
REJ09B0256-0100