SH7763 Datasheet, PDF (1112/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.4.5 I²C Bus Data Format
Figure 26.2 shows a timing chart for the I²C bus interface. Table 26.5 describes the meaning of
each symbol in figure 26.2.
IIC_SDA
IIC_SCL
1–7 8 9
S
ADDRESS R/W ACK
Start condition
1–7
8
DATA
9
ACK
1–7
8
DATA
9
P
ACK
Stop condition
Figure 26.2 I²C Bus Timing
Table 26.5 Description on Symbols of I²C Bus Data Format
Symbol
S
SLA
R/W
A
DATA
P
Description
Indicates a start condition. A master device changes SDA from high to low while
SCL is high level.
Indicates a slave address. A slave address is used when a master device selects
a slave device.
Indicates the direction of data transmission. If the R/W bit is 1, the data flows
from the slave to the master device. If the bit is 0, the data flows from the master
to the slave device.
Indicates data acknowledge. Data receiving device makes SDA low level (the
slave device returns a data acknowledge signal in master transmission mode,
and vice versa).
Indicates transmit or receive data. The data length is eight bits, which are
transferred in the MSB first.
Indicates a stop condition. A master device changes SDA from low to high while
SCL is high.
Rev. 1.00 Oct. 01, 2007 Page 1046 of 1956
REJ09B0256-0100