SH7763 Datasheet, PDF (1969/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Appendix
Appendix
A. CPU Operation Mode Register (CPUOPM)
The CPUOPM is used to control the CPU operation mode. This register can be read from or
written to the address H'FF2F0000 in P4 area or H'1F2F0000in area 7 as 32-bit size. The write
value to the reserved bits should be the initial value. The operation is not guaranteed if the write
value is not the initial value.
The CPUOPM register should be updated by the CPU store instruction not the access from
SuperHyway bus master except CPU.
After the CPUOPM is updated, read CPUOPM once, and execute one of the following two
methods.
1. Execute a branch using the RTE instruction.
2. Execute the ICBI instruction for any address (including non-cacheable area).
After one of these methods are executed, it is guaranteed that the CPU runs under the updated
CPUOPM value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RABD
INTMU
Initial value: 0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R R/W R
R
R
Rev. 1.00 Oct. 01, 2007 Page 1903 of 1956
REJ09B0256-0100