SH7763 Datasheet, PDF (1281/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Bit
7
6 to 4
3 to 0
Initial
Bit Name Value R/W
RDRE
0
R/W
—
All 0 R
RDRA[3:0] 0000 R/W
Description
Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
29.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame. SICDAR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't
care.).
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CD0E — — —
CD0A[3:0]
CD1E — — —
CD1A[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
CD0E
0
R/W Control Channel 0 Data Enable
0: Disables transmission and reception of control
channel 0 data
1: Enables transmission and reception of control
channel 0 data
14 to 12 —
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1215 of 1956
REJ09B0256-0100