SH7763 Datasheet, PDF (852/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Name
Port
RMII
0
management
data clock
RMII
management
data I/O
RMII
management
data clock
(mirror 0 pin)
RMII
management
data I/O (mirror
0 pin)
RMII
management
data clock
(mirror 1 pin)
RMII
management
data I/O (mirror
1 pin)
Link status
Wake-On-LAN
PHY interrupt
GMII transmit
clock
RMII carrier
detection
RMII receive
error
RMII receive
data
RMII receive
data
RMII transmit
enable
Abbreviation
RMII0_MDC
I/O
Output
Function
Reference clock signal for information
transfer via RMII0_MDIO in RMII mode
RMII0_MDIO
RMII0M0_MDC
I/O
Output
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode
Reference clock signal for information
transfer via RMII0M0_MDIO in RMII
mode (mirror 0 pin)
RMII0M0_MDIO I/O
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode (mirror 0 pin)
RMII0M1_MDC
Output
Reference clock signal for information
transfer via RMII0M1_MDIO in RMII
mode (mirror 1 pin)
RMII0M1_MDIO I/O
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode (mirror 1 pin)
ET0_LINKSTA
ET0_WOL
Input
Output
ET0_PHY-INT Input
GET0_GTX-CLK Output
RMII0_CRS_DV Input
Inputs link status from PHY-LSI
Signal indicating reception of Magic
Packet
Interrupt signal from PHY
Transmit signal timing reference signal in
GMII mode
Carrier detection signal in RMII mode
RMII0_RX_ER Input
RMII0_RXD0
Input
Identifies error state occurred during data
reception in RMII mode
2-bit receive data in RMII mode
RMII0_RXD1
Input 2-bit receive data in RMII mode
RMII0_TXD_EN Output
Indicates that transmit data is ready on
RMII0_TXD0 and RMII0_TXD1 in RMII
mode
Rev. 1.00 Oct. 01, 2007 Page 786 of 1956
REJ09B0256-0100