SH7763 Datasheet, PDF (218/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
Initial
Bit
Bit Name Value R/W Description
2
TI
0
R/W TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all valid
UTLB/ITLB bits. This bit is always read as 0.
1

0
R
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
0
AT
0
R/W Address Translation Enable Bit
These bits enable or disable the MMU.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is
0. In the case of software that does not use the MMU,
the AT bit should be cleared to 0.
6.2.6 Physical Address Space Control Register (PASCR)
PASCR controls the operation in the physical address space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 8
Bit Name

Initial
Value
All 0
R/W Description
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Rev. 1.00 Oct. 01, 2007 Page 152 of 1956
REJ09B0256-0100