SH7763 Datasheet, PDF (1455/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 32 PC Card Controller (PCC)
32.5 Usage Notes
(1) External Bus Frequency Limit when Using PC Card
According to the PC card standard, the attribute memory access time is specified as 600 ns (3.3
V)/300 ns (5 V). Therefore, when this LSI accesses attribute memory, the bus cycle must be
coordinated with the PC card interface timing. In this LSI, the timing can be adjusted by setting
the TED, TEH, and PCW values in the CS6BWCR register, allowing a PC card to be used within
the above frequency ranges.
The common memory access time and I/O access time (based on the IORD and IOWR signals) are
also similarly specified (see table below), and a PC card must be used within the above ranges in
order to satisfy all these specifications.
PC Card Space
Attribute memory
Common memory
I/O space
(–IORD/–IOWR pulse width)
Access Time (5 V Operation)
300 ns
250 ns
165 ns
Access Time (3.3 V Operation)
600 ns
600 ns
165 ns
(2) Pin Function Control and Card Type Switching
When setting pin function controller pin functions to dedicated PC card use ("other function"), the
disabled state should first be set in the card status change interrupt enable register
(PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the
setting has been made. However, this restriction does not apply to the card detection pins (CD1,
CD2).
When changing the card type bit (P0PCCT) in the area 6 general control register (PCC0GCR), the
disabled state should first be set in the card status change interrupt enable register
(PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the
setting has been made.
Reason: When PC card controller settings are modified, the functions of PC card pins that
generate various interrupts change, with the result that unnecessary interrupts may be
generated.
Rev. 1.00 Oct. 01, 2007 Page 1389 of 1956
REJ09B0256-0100