SH7763 Datasheet, PDF (571/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
0
WDPEI 0
SH: R/WC Write Parity Error Interrupt
PCI: R
The PERR assertion is detected during a data write
when a device other than the PCIC functions as a
bus master.
0: Write parity error interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Write parity error interrupt occurs
[Set condition]
When a write parity error interrupt is detected by the
PERR assertion.
(11) PCI Arbiter Interrupt Mask Register (PCIAINTM)
This register is the mask register for PCIAINT.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
MBIM
TBT
OIM
MBT
OIM
—
—
—
—
—
—
—
TAIM MAIM
RDP
EIM
WDP
EIM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R/W R/W R/W R R R R R R R R/W R/W R/W R/W
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 14 
Initial
Value
All 0
R/W
SH: R
PCI: R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 505 of 1956
REJ09B0256-0100