SH7763 Datasheet, PDF (791/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.5 Timer Status Registers (TSR)
The TSR registers are 16-bit registers that indicate the status of each channel. The TPU has four
TSR registers, one for each channel. The TSR registers are initialized to H'0000 by a reset, but not
initialized in standby mode, sleep mode or module standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
        TCFD  TCFU TCFV TGFD TGFC TGFB TGFA
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Bit Bit Name
15 to 8 
7
TCFD
6

5
TCFU
Initial
Value R/W Description
All 0 R
Reserved
These bits are always read as 0 and cannot be modified.
0
R
Count Direction Flag
Status flag that shows the direction in which TCNT counts in
phase counting mode of channels 2, and 3.
In channels 0 and 1, bit 7 is reserved. It is always read as 0
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
0
R
Reserved
This bit is always read as 0 and cannot be modified.
0
R/(W)* Underflow Flag
Status flag that indicates that TCNT underflow has occurred
when channels 2, and 3 are set to phase counting mode.
In channels 0 and 1, bit 5 is reserved. It is always read as 0
and cannot be modified.
[Clearing condition] (Initial value)
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to
H'FFFF)
Rev. 1.00 Oct. 01, 2007 Page 725 of 1956
REJ09B0256-0100