SH7763 Datasheet, PDF (1009/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Initial
Bit
Bit Name Value R/W
27
TFE
0
R/W
26
TWBI
0
R/W
25 to 12 
All 0 R
11 to 0 TFS[11:0] All 0 R/W
Description
Transmit Frame Error Occurrence
Indicates that an error occurred in the transmit frame.
0: The TFS11 to TFS0 bits are all 0
1: One of the TFS11 to TFS0 bits is 1
The TFS8 to TFS0 bits can be masked for each factor by
using TRSCER. TheTFS11 to TFS9 bits cannot be
masked.
This bit is set by the E-DMAC write-back operation.
Write-Back Completion Interrupt Notification
0: Does not notify of a write-back completion interrupt
1: After a write-back operation to this descriptor is
complete, this bit sets the TWB1 and TWB0 bits in
EESR to 11 and notifies the CPU of a write-back
completion interrupt.
This bit is valid only for the descriptor including the end of
transmit frame (TFP = 01 or 11). This bit is cleared to 0 by
the E-DMAC write-back operation.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Frame Status
These bits indicate the status of the corresponding frame.
A bit below, which is set by the E-DMAC write-back
operation, indicates the occurrence of the corresponding
event when set to 1.
• TFS[11:10]: Reserved (The write value should always
be 0.)
• TFS[9]: Transmit FIFO underflow (Corresponding to
the TUC bit in EESR)
• TFS[8]: Detection of transmission abort
(Corresponding to the TABT bit in EESR)
• TFS[7:0]: Reserved (The write value should always be
0.)
Rev. 1.00 Oct. 01, 2007 Page 943 of 1956
REJ09B0256-0100