SH7763 Datasheet, PDF (351/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Module Bit
SCIF0
3
2
1
0
Section 9 Interrupt Controller (INTC)
Source Function
Description
TXI0
BRI0
RXI0
SCIF channel 0 transmit FIFO data Indicates SCIF interrupt
empty interrupt
sources. This register
SCIF channel 0 break interrupt or
overrun error interrupt
indicates the SCIF
interrupt sources even if
mask setting is made in
SCIF channel 0 receive FIFO data full the interrupt mask
interrupt or receive data ready
register for them.
interrupt
ERI0 SCIF channel 0 receive error interrupt
INT2B3: Indicates detailed interrupt sources for the DMAC.
Module
DMAC
Bit
Source Function
Description
31 to 13 —
12
DMAE
11 to 6 —
These bits are always read as 0. The
write value should always be 0.
DMA channels 0 to 5 address error
interrupt
These bits are always read as 0. The
write value should always be 0.
Indicates DMAC
interrupt sources. This
register indicates DMAC
interrupt sources even if
mask setting is made in
the interrupt mask
register for them.
5
DMTE5 Channel 5 DMA transfer end interrupt
4
DMTE4 Channel 4 DMA transfer end interrupt
3
DMTE3 Channel 3 DMA transfer end interrupt
2
DMTE2 Channel 2 DMA transfer end interrupt
1
DMTE1 Channel 1 DMA transfer end interrupt
0
DMTE0 Channel 0 DMA transfer end interrupt
Rev. 1.00 Oct. 01, 2007 Page 285 of 1956
REJ09B0256-0100