SH7763 Datasheet, PDF (724/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
WDTBCNT is an 18-bit up-counter operated on the peripheral clock0 (Pck0). WDTBCNT is
cleared when H'55 is set to the bits 31 to 24 in WDTBST.
If the peripheral clock frequency is 66.6 MHz, the WDTBCNT overflow time is approximately
3.932 ms (= 2^18 [bit] × 1/66.6 [MHz]).
WDTCNT is a 12-bit counter, starts count up operation when overflow occurs in WDTBCNT. The
time until WDTCNT overflows becomes the maximum value when H'000 is set to WDTST.
Where the peripheral clock frequency is 66.6 MHz, the maximum overflow time is approximately
16.105 s (= 2^12 [bit] × 3.932 [ms]).
And the time until WDTCNT overflows becomes the minimum value when H'5A000001 is set to
WDTST. The minimum overflow time is approximately 3.932 ms (= 2^1 [bit] × 3.932 [ms]).
17.4.5 Clearing WDT Counter
Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow
setting value to WDTST clears WDTCNT.
Rev. 1.00 Oct. 01, 2007 Page 658 of 1956
REJ09B0256-0100