SH7763 Datasheet, PDF (33/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)................................................................1585
37.1 Features............................................................................................................................ 1585
37.2 Input/Output Pins ............................................................................................................. 1587
37.3 Register Configuration..................................................................................................... 1588
37.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1591
37.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1593
37.3.3 LCDC Data Format Register (LDDFR).............................................................. 1596
37.3.4 LCDC Scan Mode Register (LDSMR) ............................................................... 1598
37.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1599
37.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ......... 1601
37.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1602
37.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1603
37.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1604
37.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1605
37.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ....................................... 1606
37.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1607
37.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1608
37.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1609
37.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1610
37.3.16 LCDC Interrupt Control Register (LDINTR) ..................................................... 1611
37.3.17 LCDC Power Management Mode Register (LDPMMR) ................................... 1614
37.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1616
37.3.19 LCDC Control Register (LDCNTR)................................................................... 1618
37.3.20 LCDC User Specified Interrupt Control Register (LDUINTR).......................... 1619
37.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ........... 1621
37.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ........................ 1622
37.4 Operation ......................................................................................................................... 1623
37.4.1 LCD Module Sizes which can be Displayed in this LCDC ................................ 1623
37.4.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected
Memory (SDRAM)............................................................................................. 1625
37.4.3 Color Palette Specification ................................................................................. 1628
37.4.4 Data Format ........................................................................................................ 1629
37.4.5 Setting the Display Resolution............................................................................ 1633
37.4.6 Power-Supply Control Sequence ........................................................................ 1633
37.4.7 Operation for Hardware Rotation ....................................................................... 1638
37.5 Clock and LCD Data Signal Examples............................................................................ 1641
37.6 Usage Notes ..................................................................................................................... 1653
37.6.1 Procedure for Halting Access to Display Data Storage VRAM
(DDR-SDRAM in Area 3) .................................................................................. 1653
Rev. 1.00 Oct. 01, 2007 Page xxxiii of lxvi